`timescale 1 ns / 1 ps
module tb
(

);

parameter PERIOD = 20 ;


reg      pll_rst;
wire   	tx_rx;
wire		clk_10M;
wire		pll_locked;


wire     rst=!pll_locked;

reg				 tx_vld;
reg				 tx_done;

reg				 ki;
reg      [7:0]  tx_data;
reg		[7:0]  frame_len;//frame length 
reg		[2:0]  frame_st;
reg		[3:0]  frame_interval;


reg inclk ;

   initial begin
      inclk = 1'b0;
      #(PERIOD/2);
      forever
         #(PERIOD/2) inclk = ~inclk;
   end


	initial begin
	pll_rst=1'b1;
	tx_data=0;
	#50 pll_rst=1'b0;
	end
	
	
	
always@(posedge clk_10M or posedge rst)
if(rst) begin
	tx_vld		<=1'b0;
	tx_done		<=1'b0;
	frame_len	<=0;
	ki				<=1'b0;
	tx_data		<=0;
	frame_st		<=0;  //frame state machine
	frame_interval<=0;
end
else  case(frame_st)
0:begin
	
	tx_vld		<=1'b0;
	tx_done		<=1'b0;
	ki				<=1'b0;			
	tx_data		<=0;
	frame_interval<=frame_interval+1;
	if(frame_interval==15)
	frame_st		<=1;
	
   end
1:begin  //start 1
   frame_interval<=0;
	frame_len	<=0;
	frame_st		<=2;
	tx_vld		<=1'b1;
	tx_done		<=1'b0;
	ki				<=1'b1;
	tx_data		<=8'hbc;
end


2:begin  //start 1
	frame_len	<=0;
	frame_st		<=3;
	tx_vld		<=1'b1;
	tx_done		<=1'b0;
	ki				<=1'b0;
	tx_data		<=8'h00;
end

3:begin
	frame_len<=frame_len+1;
	tx_vld		<=1'b1;
	tx_data<=tx_data+1;
	if(frame_len==15)begin
	frame_st<=4;
	ki				<=1'b1;
	tx_data		<=8'h3c;
	end
end
4:begin
	frame_st		<=5;
	tx_vld		<=1'b0;
	tx_done		<=1'b1;
	tx_data		<=8'h0;
	end
5:begin
	frame_st		<=0;
	tx_vld		<=1'b0;
	tx_done		<=1'b0;
	ki				<=1'b0;			
	tx_data		<=0;
	
   end
default:frame_st<=3;
endcase


lvds_top   lvds_top_inst
(
.inclk			(inclk),
.pll_rst			(pll_rst),
.tx_vld			(tx_vld),
.tx_done			(tx_done),
.ki				(ki),
.tx_data			(tx_data),
.tx				(tx_rx),
.rx				(tx_rx),
.clk_10M			(clk_10M),
.pll_locked		(pll_locked)

);


endmodule

